Multi-layer device

ABSTRACT

A multi-layer device is provided for connecting to an electrical unit enclosed within the multi-layer device. A first wafer has a first outer terminal and a second outer terminal with etch pits. A first insulator has a first surface bonded to the first wafer and a first inner terminal located on an opposing second surface. A second wafer has a first surface bonded to the second surface of the first insulating layer and includes a pillar electrically connected to the first wafer. A second insulator has a first surface bonded to a second surface of the second wafer and a second inner terminal located on the first surface of the second insulator. The first outer terminal is electrically connected to the first inner terminal, and the second outer terminal is electrically connected to the second inner terminal. The first and second outer terminals are adapted for connecting to an electrical unit. A reinforcement is positioned adjacent to at least one of the first and second outer and, inner terminals to provide for reinforcement of the at least one of the first and second outer and inner terminals.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to multi-terminal, multi-layer devices,and more particularly to multi-terminal, multi-layer devices, which canwithstand greater mechanical shocks or mechanical loads to theirterminals.

2. Description of the Related Art

In certain applications, electrical devices or sensors are used tomeasure or detect various operating or performance parameters such as,for example, temperature, pressure, or acceleration. These devices canbe actuators or electronic devices such as magnetic field sensors.Typically, the electrical functions of the devices are communicated tosupport electronics and/or some recording apparatus that allows anoperator to monitor the parameters being measured by the sensors. Inmany instances, the device is provided with terminals, which are simplyconnected to lead wires extending from the support electronics orrecording apparatus.

Some electronic devices are made of multiple layers of semiconductormaterial. These devices or sensors typically include an interioroperating unit. The electrical function of the unit may occur at variouslayers of the device, which must be connected, to the externalelectronics. For example, lead wires may be connected to interiorterminals on one or more surfaces of the interior operating unit, andthen fed through access holes in the layers to the outside of thedevice. However, when electrical functions are communicated fromsurfaces on opposite sides, for example, an upward and a downwardsurface, of the interior operating unit, wiring to the unit becomesinconvenient during the assembly process.

Some assembly processes use a “flip-chip” technique in which the innerterminals of the interior operating unit are presented on one surface.Patterns of conductor lines extend from the inner terminals up aninsulated surface of a semiconductor layer that is adjacent to theinterior operating unit to an outer surface of the semiconductor layer.It has been proposed to electrically connect the interior operating unitto the outside by using metal thin films that coat oxide-insulated holesof semiconductor layers positioned next to the interior operating unit.Such connections, however, introduce large capacitance coupling whichcan be troublesome, for example, for systems working at radiofrequencies. Furthermore, extending the conductor lines through severallayers is not easily accomplished.

There is a need to provide an improved multi-terminal, multi-layerdevice. There is a further need to provide an improved multi-terminal,multi-layer device, which can withstand greater mechanical shocks ormechanical loads to its terminals.

SUMMARY

Accordingly, an object of the present invention is to provide animproved multi-terminal, multi-layer device.

Another object of the present invention is to provide a multi-terminal,multi-layer device that can withstand greater mechanical shocks ormechanical loads to its terminals.

Yet another object of the present invention is to provide amulti-terminal, multi-layer device with reinforcements positionedadjacent to delicate terminals.

Another object of the present invention is to provide a multi-terminal,multi-layer device with improved electrical insulation of its terminals.

A further object of the present invention is to provide amulti-terminal, multi-layer device with a reduced chance ofcontamination and a reduced potential of electrical shorts betweenterminals.

These and other objects of the present invention are achieved in amulti-layer device for connecting to an electrical unit enclosed withinthe multi-layer device. A first wafer has a first outer terminal and asecond outer terminal. A first insulator has a first surface bonded tothe first wafer and a first inner terminal located on an opposing secondsurface. A second wafer has a first surface bonded to the second surfaceof the first insulating layer and includes a pillar electricallyconnected to the first wafer. A second insulator has a first surfacebonded to a second surface of the second wafer and a second innerterminal located on the first surface of the second insulator. The firstouter terminal is electrically connected to the first inner terminal,and the second outer terminal is electrically connected to the secondinner terminal. The first and second outer terminals are adapted forconnecting to an electrical unit. A reinforcement is positioned adjacentto at least one of the first and second outer and inner terminals toprovide for reinforcement of the at least one of the first and secondouter and inner terminals.

In another embodiment of the present invention, a multi-layer device hasa first wafer with a first outer terminal and a second outer terminal. Afirst insulator has a first surface bonded to the first wafer and afirst inner terminal located on a second surface. A second waferincludes a first surface bonded to the second surface of the firstinsulating layer and has a pillar electrically connected to the firstinsulator. A second insulator has a first surface bonded to a secondsurface of the second wafer and a second inner terminal located on thatfirst surface. A third wafer has a cap electrically connected to thesecond insulator. An electrical unit is positioned between the firstwafer and the third wafer and is electrically connected to the first andsecond inner terminals. A reinforcement is positioned adjacent to atleast one of the first and second inner and outer terminals to providefor reinforcement of the at least one of the first and second inner andouter terminals.

In another embodiment of the present invention, a multi-layer deviceincludes a first wafer with a first outer terminal and a second outerterminal. An interior operating unit has a first inner terminalelectrically connected through the first wafer to the first outerterminal, and a second inner terminal electrically connected through thefirst wafer to the second outer terminal. A third wafer is provided. Theinterior operating unit is hermetically sealed between the lid and thethird wafer. A reinforcement is positioned adjacent to at least one ofthe first and second outer terminals to provide for reinforcement of theat least one of the first and second outer terminals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a multi-layer silicon device withterminals in accordance with the invention.

FIG. 2A is a side view of a multi-layer silicon device with internalterminals connected to an electrical unit enclosed within the device inaccordance with the invention.

FIG. 2B is a top view of the device along the line 2B-2B of FIG. 2A.

FIG. 2C is a bottom view of the device along the line 2C-2C of FIG. 2A.

FIG. 2D is an end view of the device along the line 2D-2D of FIG. 2B.

FIG. 3A is a side of an alternative embodiment of the multi-layersilicon device with internal terminals in accordance with the invention.

FIG. 3B is a top view of the device along the line 3B-3B of FIG. 3A.

FIG. 3C is a bottom view of the device along the line 3C-3C of FIG. 3A.

FIG. 3D is an end view of the device along the line 3D-3D of FIG. 3A.

FIG. 3E is an end view of the device along the line 3E-3E of FIG. 3A.

FIG. 4A is a side view of another alternative embodiment of themulti-layer silicon device with internal terminals in accordance withthe invention.

FIG. 4B is a top view of the device along the line 4B-4B of FIG. 4A.

FIG. 4C is a bottom view of the device along the line 4C-4C of FIG. 4A.

FIG. 4D is an end view of the device along the line 4D-4D of FIG. 4B.

FIGS. 5A-5F are schematics of a sequence of steps to fabricate an etchpit of the devices in accordance with the invention.

FIG. 6 is a perspective view of the device of FIG. 1 with a mechanicalreinforcement positioned in a surrounding relationship to the terminals.

FIG. 7 is a flow diagram of a sequence of steps to fabricate the devicein accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, one embodiment of a two-terminal multi-layer device10 of the present invention is shown which can enclose an interiorelectrical unit 12. The multi-layer device 10 can be a sensor tomeasure, for example, temperature, pressure, or acceleration. Themulti-layer device 10 can also be used as an actuator or as some otherelectronic device such as a magnetic field sensor. Electrical signalsare transmitted to and from the interior unit 12 to the outside of themulti-layer device 10 through the two outer terminals 14 and 16 that arecoated with a thin layer of metal 17.

The metal layer 17 on each outer terminal 14 and 16 can be connected,for example, to a pair of lead wires 18 and 20, respectively, whichextend to a monitor, recording apparatus, and/or support electronics. Aparticular feature of the multi-layer device 10 is that the interiorunit 12 can be hermetically sealed within the multi-layer device 10 toprotect the interior unit 12 from the outside environment.

The multi-layer device 10 can include a third wafer 22, a first wafer24, and a second wafer 26 made from, for example, silicon. The thirdwafer 22 and the first wafer 24 are each bonded to an outer surface of arespective layer of Pyrex 28 and 30, or any other suitable insulatingmaterial, while the inner surfaces of the Pyrex layers 28 and. 30 arebonded to the opposite sides of the second wafer 26.

The outer terminals 14 and 16 are essentially isolated islands separatedphysically and electrically from the remainder of the third wafer 22 bya set of trenches 32. The first wafer 24 has a cap 34.

As illustrated in FIG. 1, a reinforcement can be included in thetrenches 32 to provide reinforcement for at least a portion of the outerterminals 14, 16, as well any other terminals on the outer surface ofwafer 22, as well as any other terminals on an outer surface of otherwafers that are exposed to potential damage from mechanical or otherforces, collectively “the “Terminals”. The reinforcement is at least apartial encapsulation of the Terminals in order to provide thereinforcement and reduce damage to the Terminals from mechanical andother forces. The reinforcement also reduces mechanical loads to theTerminals.

The reinforcement can also provide improved electrical insulation of atleast a portion of the Terminals. Further, the reinforcement can alsoreduce a chance of contamination and a reduced potential of electricalshorts between the Terminals.

The reinforcement can be made of an insulator, including but not limitedto, glass, polymers and the like. The reinforcement can have thefollowing dimensions, 25-500 microns as a width in the trench 32 itself,and at least 50% and not more than 100% of the first wafer 24 in height,but does not cover the top surface of the Terminals.

Optionally, each of the terminals 14 and 16 has a recessed region 38provided with a protrusion 40. The protrusions 40 of the terminals 14and 16 are in electrically contact with a first etch pit 42 and a secondetch pit 44 of the Pyrex layer 28, respectively. The cap 34 and thesecond wafer 26 are also provided with the recessed regions 38 andprotrusions 40 such that the cap 34 is electrically connected to a firstetch pit 50 and a second etch pit 52 of the second layer of Pyrex 30,while a portion of the second wafer 26 is electrically connected to the,second etch pit 44 of the Pyrex layer 28, and the second etch pit 52 ofthe second Pyrex layer 30.

The first etch pits 42 and 50 are further electrically connected to apair of inner thin-film terminals 54 and 56 that coat the inner surfacesof the layers of Pyrex 28 and 30, respectively. The protrusions 40ensure a controlled area of contact between the etch pits and theadjacent layer of silicon. Alternatively, the terminals 14 and 16, thesecond wafer 26, and the cap 34 do not have a recessed region. Rather,they can be in direct contact with a respectively layer Pyrex. Forexample, there is shown in FIG. 5F an outer terminal without a recessedregion.

Accordingly, when the multi-layer device 10 is assembled, there is anelectrical path from the first terminal 14 through the first etch pit 42of the Pyrex layer 28 to the inner terminal 54. There is also a secondelectrical path from the second terminal 16 through the second etch pit44 of the Pyrex layer 28.to a pillar 58 of the second wafer 26. Thepillar 58 is electrically isolated from the remainder of the secondwafer 26 by a gap 60 so that the second electrical path continuesthrough the second etch pit 52 of the Pyrex layer 30, across the cap 34,up the first etch pit 50 of the Pyrex layer 30, and finally to theterminal 56.

With the inner terminals 54 and 56 connected to the interior unit 12which is electrically isolated from the second wafer 26 by a gap 60 b,electrical signals to and from the interior unit 12 are communicated tothe outside of the multi-layer device 10 via the outer terminals 14 and16.

The third wafer 22, first wafer 24, and second wafer 26 and the twolayers of Pyrex 28 and 30 are each about 0.4 mm thick, and themulti-layer device 10 itself is about 2 mm thick, 2.5 mm long, and 1 mmwide. The thin layer of metal 17 on each of the terminals 14 and 16 ismade from any suitable conductive material such as, for example, gold orplatinum, and has a thickness of about 1 micron. The etch pits 42, 44,50, and 52 are also coated with a thin layer of metal of about 1 micronwhich makes the electrical connection through the respective layer ofPyrex 28 and 30, and the inner terminals 54 and 56 are about 0.75 micronthick. As with the terminals 14 and 16, the metal for the etch pits 42,44, 50, and 52 and the inner terminals 54 and 56 can be made anysuitable conductive material such as gold or platinum. The metal foretch pits 42, 44, 50, and 52 can also be a base metal such as aluminum.

The embodiment shown in FIG. 1 is a two-terminal device. However, otherembodiments can be used to enclose the interior unit 12. For example,there is shown in FIGS. 2A-2D a three-terminal multi-layer device 100that is made of the three silicon layers, the third wafer 22, the firstwafer 24, and the second wafer 26, as well as the two insulating layersof Pyrex 28 and 30.

Similar to the multi-layer device 10 shown in FIG. 1, the multi-layerdevice 100 is provided with two outer terminals 14 and 16 which areelectrically isolated from the rest of the third wafer 22 by a set oftrenches 32. Accordingly, there is an electrically conductive path fromthe first terminal 14 to the inner terminal 54 through the etch pit 42of the layer of Pyrex 28, and another conductive path from the secondterminal 16 through the second etch pit 44 of the Pyrex layer 28 to thepillar 58 of the second wafer silicon layer 26, and then from the pillar58 through the second etch pit 52 of the second layer of Pyrex 30,across the cap 34 electrically isolated from the remainder of the firstwafer 30 by the trenches 36, up the first etch pit 50 of the Pyrex layer30, and to the inner terminal 56 that coats the inner surface of thePyrex layer 30. Typically, the regions of the second wafer 26 adjacentthe inner terminals 54 and 56 are recessed so that those regions are notin direct contact with the inner terminals 54 and 56.

The multi-layer device 100 also includes a third terminal 102electrically isolated from the third wafer 22 by the trenches 32 andcoated with a thin layer of metal such as the metal layer 17 shown inFIG. 1. In this embodiment, a portion 104 of the second wafer 26functions as a third inner terminal. The portion 104 includes all of thesecond wafer layer 26 except that which is isolated as the pillar 58,and is electrically connected to the third terminal 102 of the thirdwafer 22 through a third etch pit 106 of the Pyrex layer 28. Hence, withthe multi-layer device 100, electrical functions to and from theinterior unit 12 are transmitted between the three inner terminals 54,56, and 104 connected to the interior unit 12 and the outside of themulti-layer device 100 via the outer terminals 14, 16, and 102 along therespective conductive paths between the inner terminals and the outerterminals. Additionally, the region of the third wafer 22 isolated fromthe outer terminals 14,16, and 102 can serve as another terminal, forexample, by providing that region with its own metal film terminal.Similarly, the first wafer 24 that is isolated from the cap 34 can alsoserve as an additional terminal by making connections to that isolatedportion with a metal film terminal.

Referring now to FIGS. 3A-3E, there is shown a four-terminal device 200.As with the multi-layer device 100, the device 200 includes three outerterminals 14,16, and 102 connected along a respective conductive path tothe three inner terminals 54, 56, and 104, the paths being identicallylabeled to those shown in FIGS. 2A-2D. However, in this configuration,the third wafer 22 includes a fourth terminal 202. Although the fourthterminal 202 is isolated from the rest of the third wafer 22 by thetrenches 32, there is a metal film connector 203 that electricallyconnects the fourth terminal 202 to the portion 201 a. Similarly, thefirst wafer 24 includes a terminal 204, isolated by the trenches 36,electrically connected to the portion 201 b of the first wafer with aconnector 206. Further, there is an electrical path from the third wafer22 to a second pillar 208 of the second wafer 26 through a fourth etchpit 210 of the Pyrex layer 28, and from the second pillar 208 to thefirst wafer 24 via a third etch pit 212 of the Pyrex layer 30. Thus, theportion 201 a and the outer terminal 202 of the third wafer 22 iselectrically connected to the portion 201 b and the outer terminal 204of the first wafer 24 such that they serve as guard electrodes.

In other embodiments, rather than using layers of Pyrex to insulate thethird wafer 22, the first wafer 24, and the second wafer 26 from eachother, other types of insulators can be used. For instance, there isshown in FIGS. 4A-4D a three-terminal device 300 with the third wafer 22separated from the second wafer 26 by a thin oxide layer 302, while thefirst wafer 24 is separated from the second wafer 26 by a second thinoxide layer 304. In this embodiment, the oxide layers 302 and 304 aremade of SiO.sub.2, for example, and have a thickness of about 1.2 to 1.4microns.

The third wafer 22 of the device 300 is provided with a set of outerterminals 302 and two other outer terminals 304 and 306. The terminals304 and 306 are islands separated from the rest of the third wafer 22 bythe trenches 32, while the terminals 302 are electrically connectedacross the rest of the third wafer 22. That is, the entire portion ofthe third wafer 22 isolated from the terminals 304 and 306 function as aterminal.

The second wafer 26 is provided with a portion 308 and a pillar 310. Theportion 308 is electrically continuous throughout the second wafer 26except for the isolated pillar 310, and includes a sealed rim thatsurrounds the interior unit 12. The oxide layer between the terminal 304and the portion 308 is interrupted with a metal film to provide aconductive path between the terminal 304 and the portion 308. Hence, theportion 308 functions as an inner terminal, which is electricallyconnected to the terminals 304. In addition, the layer of oxide oneither side of the pillar 310 is interrupted with a respective metalfilm such that there is a conductive path from the terminal 306 throughthe pillar 310 to the first wafer 24 themselves. The interior unit 12 isdirectly connected to the outer terminal 302, as well as the portion308, and the first wafer 24, and hence to the terminals 304 and 306,respectively.

Referring now to FIGS. 5A-5F, there is shown a sequence of illustratedsteps to fabricate an etch pit through a layer of Pyrex such as thelayer 28. First (FIG. 5A), the Pyrex layer 28 is bonded to a layer ofsilicon, for example, the third wafer 22, by anodic bonding. Thisbonding process uses heat and electricity, and optionally pressure, sothat an electrical charge attracts the Pyrex to the silicon and thephysical contact between the two layers causes a chemical reaction withthe Pyrex. At the interface, the Pyrex is reduced and the silicon isoxidized. The newly formed oxide is as adherent to the silicon asthermally grown oxide, and is continuous with the Pyrex.

As shown in FIG. 5B, the Pyrex 28 is optionally polished to clean itsouter surface. Subsequently, as illustrated in FIG. 5C, a metal layer406 is applied to this surface, and a photochemical etching process isused to create the desired pattern with the appropriate openings 407.

An impact grinder is used to pierce the Pyrex 28, through the openings407, as in FIG. 5D, to create the holes 408. The impact grinder is anultrasonic tool shaped with protrusions located where holes in the Pyrexare desired. The impact grinder uses ultrasonic vibrations to grind thePyrex into slurry that is flushed away.

Another layer of metal 410 is applied to electrically connect the firstlayer of metal 407 to the third wafer 22 as illustrated in FIG. 5E.Finally another photochemical etching process is used to create theisolated islands 412, which serve as the terminals of the third wafer22, FIG. 5F.

In other embodiments, the layer of Pyrex is preformed with the desiredholes before it is bonded to the layer of silicon, and then after thebonding process, the layer of metal is applied to make the electricallyconnection from one side of the Pyrex to the other side of the Pyrexadjacent to the layer of silicon. As shown in FIGS. 5D through 5F, thehole 408 of the etch pit is cylindrical. Alternatively, the holes canhave a conical shape, for example, as shown in FIG. 1. The conical holesfor the etch pits 42, 44, 50, and 52 can be produced with aphotochemical etching process. The surface of the holes are then coatedwith the metal layer 410 to electrically connect to a layer of metal 409in contact with the protrusions 40.

Referring now to FIG. 7, there is shown a flow diagram of a sequence ofsteps 500 to make the devices 10, 100, or 200.

First, in a step 502, a wafer of Pyrex is bonded to a wafer of siliconfrom which the third wafer 22 or the first wafer 24 are formed. Next, ina step 504, the etch pits are formed as described earlier. The desiredholes in the wafers of Pyrex can be preformed or they can be made withthe ultrasonic grinding process described above. In addition, a layer ofmetal is applied to the inner surfaces of the Pyrex wafers to form theinner terminals 54 and 56.

Then, in a step 506, the silicon wafers are put through a photochemicaletching process to form the outer terminals in the third wafer 22 or thefirst wafer 24, as well as the cap 34 of the first wafer 24.

Subsequently, in a step 508, another photochemical etching process isused to form the appropriate pillars of the second wafer 26 from anotherwafer of silicon. The interior operating unit 12 is also fabricatedduring this step.

Next, in a step 510, the second wafer 26 is bonded to the two layers ofPyrex 28 and 30. Then, in a step 512, metal is selectively applied tothe outer terminals.

Finally, in a step 514, the desired device is sawed or cut away from therest of the silicon and Pyrex wafers. Note, that typically about 40 to1000 individual devices can be formed from these wafers. That is, eachof the devices is essentially a die in the wafers during the fabricationprocess. Although the pillars are originally projections from aneighboring die, the sawing process cuts the pillar free from theneighbor thereby forming the isolated pillars of the individual devicesbonded only to adjacent layers of that particular device.

The process to form the device 300 shown in FIGS. 4A-4D is somewhatdifferent than that illustrated in FIG. 6. To fabricate the device 300,the oxide layers 302 and 304 are first applied to the respective layersof silicon, which ultimately form the third wafer 22 and the first wafer24. Then, a third wafer of silicon is subjected to a photochemicaletching process to form the pillar of the second wafer 26. The thirdwafer 22 is also etched to form the isolated regions in the third wafer22, which serve as the outer terminals. Subsequently, the third water22, the first wafer 24, and the second wafer 26 are bonded together witha solder bonding process. That is, a metal film, such as, for example, agold film, is applied only where a conductive path is desired betweenthe various layers. Upon being heated, this film layer melts and sticksor fuses to the layers, thereby bonding the layers together. Finally,the conductive metal layer 17 is applied to certain isolated regions ofthe third wafer 22 to metalize the outer terminals.

The following process can make the reinforcement:

The first wafer 24 is first etched on a side A to a desired depth thatis no more than 90% of the thickness of the first wafer 24.

The etched first wafer 24 is then filled with the material of thereinforcement and then polished to make it planar. The first wafer 24 isthen bonded to the second wafer 26. A second etch is then performed onthe opposite side B of the first wafer 24.

While this invention has been particularly shown and described withreferences to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the scope of the inventionencompassed by the appended claims.

1. A multi-layer device for connecting to an electrical unit enclosedwithin the multi-layer device, comprising: a first wafer having a firstouter terminal and a second outer terminal; a first insulator having afirst surface bonded to the first wafer and a first inner terminallocated on an opposing second surface; a second wafer having a firstsurface bonded to the second surface of the first insulating layer andincluding a pillar electrically connected to the first wafer; a secondinsulator having a first surface bonded to a second surface of thesecond wafer and a second inner terminal located on the first surface ofthe second insulator, the first outer terminal being electricallyconnected to the first inner terminal, the second outer terminal beingelectrically connected to the second inner terminal, the first andsecond outer terminals being adapted for connecting to an electricalunit; and a reinforcement positioned adjacent to at least one of thefirst and second outer and inner terminals to provide for reinforcementof the at least one of the first and second outer and inner terminals.2. The device of claim 1, wherein the reinforcement reduces mechanicalloads to the at least one of the first and second outer and innerterminals.
 3. The device of claim 1, wherein the reinforcement ispositioned to provide at least a partial encapsulation of the at leastone of the first and second outer and inner terminals.
 4. The device ofclaim 1, wherein the reinforcement reduces mechanical loads to the atleast one of the first and second outer and inner terminals.
 5. Thedevice of claim 1, wherein the reinforcement provides improvedelectrical insulation of at least a portion of the at least one of thefirst and second outer and inner terminals.
 6. The device of claim 1,wherein the reinforcement reduces a chance of contamination and areduced potential of electrical shorts between at least two of the firstand second outer and inner terminals.
 7. The device of claim 1, furthercomprising: a third wafer electrically connected to the second waferwith a first surface to is connected to the second insulator.
 8. Thedevice of claim 1, wherein the reinforcement is positioned in a trenchformed adjacent to the first and second outer and inner terminals. 9.The device of claim 1, wherein the reinforcement is made of glass. 10.The device of claim 1, wherein the reinforcement has a width of about25-500 microns.
 11. The device of claim 1, wherein the reinforcement hasa height of about 50% to no more than 100% of the height of the firstwafer.
 12. The device of claim 7, wherein the third wafer includes athird outer terminal, the reinforcement further positioned adjacent tothe third outer terminal.
 13. The device of claim 12, wherein the thirdwafer includes a fourth outer terminal, the second wafer includes asecond pillar, and the first wafer includes a fifth outer terminal, thesecond pillar being electrical connected to a portion of the thirdwafer, and the fifth outer terminal being electrically connected to aportion of the first wafer so that the portions of the third wafer andfirst wafer, and the fourth and fifth outer terminals serve as guardelectrodes., the reinforcement further positioned adjacent to the thirdand fifth outer terminals
 14. A multi-layer device for connecting to anelectrical unit enclosed within the multi-layer device, comprising: afirst wafer having a first terminal and a second terminal, and an innersurface with a first insulator; a second wafer having a first surfacebonded to the first insulator and a second surface bonded to a secondinsulator, and including a pillar electrically connected to the secondterminal; and a third wafer having an inner surface bonded to the secondinsulator and a portion being electrically connected to the pillar, thefirst wafer and the third wafer being adapted for electricallyconnecting to an electrical unit; and a reinforcement positionedadjacent to at least one of the first and second terminals to providefor reinforcement of the at least one of the first and second terminals.15. The device of claim 14, wherein the first wafer, the third wafer,and the second wafer are made of silicon.
 16. The device of claim 14,wherein the first and second insulators are made of SiO₂.
 17. The deviceof claim 14, wherein the electrical unit is hermetically sealed withinthe device.
 18. The device of claim 14, wherein the first wafer includesa third terminal in electrical contact with a portion of the secondwafer, the portion of the second wafer being adapted for electricallyconnecting to the electrical unit.
 19. The device of claim 18, whereinthe first, second, and third terminals are coated with a conductivemetal.
 20. The device of claim 19, wherein the metal is gold.
 21. Thedevice of claim 19, wherein the metal is platinum.
 22. A multi-layerdevice, comprising: a first wafer having a first outer terminal and asecond outer terminal; a first insulator having a first surface bondedto the first wafer and a first inner terminal located on a secondsurface; a second wafer having a first surface bonded to the secondsurface of the first insulating layer and including a pillarelectrically connected to the first insulator; a second insulator havinga first surface bonded to a second surface of the second wafer and asecond inner terminal located on that first surface; a third waferhaving a cap electrically connected to the second insulator; anelectrical unit positioned between the first wafer and the third waferand electrically connected to the first and second inner terminals; anda reinforcement positioned adjacent to the first and second outerterminals to provide for reinforcement of the first and secondterminals.
 23. The device of claim 22, wherein the first wafer, thethird wafer, and the second wafer are made of silicon.
 24. The device ofclaim 22, wherein the first and second insulators are made of Pyrex. 25.The device of claim. 22, wherein the electrical unit is hermeticallysealed within the device.
 26. The device of claim 22, wherein the firstand second terminals are coated with a conductive metal.
 27. The deviceof claim 26, wherein the metal is gold.
 28. The device of claim 26,wherein the metal is platinum.
 29. The device of claim 22, wherein thefirst wafer includes a third outer terminal, and a portion of the secondwafer serves as a third inner terminal electrically connected to theelectrical unit.
 30. The device of claim 29, wherein the first waferincludes a fourth outer terminal, the second wafer includes a secondpillar, and the third wafer includes a fifth outer terminal, and thefourth and fifth outer terminals serve as guard electrodes.
 31. Amulti-layer device, comprising: a first wafer having a first outerterminal and a second outer terminal; an interior operating unit havinga first inner terminal electrically connected through the first wafer tothe first outer terminal, and a second inner terminal electricallyconnected through the first wafer to the second outer terminal; a thirdwafer, the interior operating unit being hermetically sealed between thelid and the third wafer; and a reinforcement positioned adjacent to atleast one of the first and second outer terminals to provide forreinforcement of the at least one of the first and second outerterminals.